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Espressif Systems /ESP32-C6 /PCR /UART1_SCLK_CONF

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Interpret as UART1_SCLK_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0UART1_SCLK_DIV_A 0UART1_SCLK_DIV_B 0UART1_SCLK_DIV_NUM 0UART1_SCLK_SEL 0 (UART1_SCLK_EN)UART1_SCLK_EN

Description

UART1_SCLK configuration register

Fields

UART1_SCLK_DIV_A

The denominator of the frequency divider factor of the uart1 function clock.
UART1_SCLK_DIV_B

The numerator of the frequency divider factor of the uart1 function clock.
UART1_SCLK_DIV_NUM

The integral part of the frequency divider factor of the uart1 function clock.
UART1_SCLK_SEL

set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL.
UART1_SCLK_EN

Set 1 to enable uart0 function clock

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data